The invention relates to a non-volatile semiconductor memory device with an electrically erasable and programmable read only memory showing a high speed batch erasure operation.
The electrically erasable and programmable read only memory shows a batch erasure of all informations stored in all of memory cells provided therein by receiving high voltage erasing signals for a predetermined time sufficient for implementation of the batch erasure. The batch erasure means an erasure at one time of all informations stored in all the memory cells. The batch erasure operation should be implemented to prevent an excess application of the erasure signal to the memory cells after all the informations of the memory cells have already been erased. If the erasure signal is still kept applied to the memory cells alter all the informations stored therein were erased, all the memory cells comes into an excess erased state wherein a threshold voltage of the memory cells has a negative value thereby the memory cells become unoperational and unusable. To prevent this problem, it is required to apply the erasure signal to the memory cells together with confirming the erasure state of the memory cells.
In the prior art to which the invention pertains, it has been proposed to implement repeating and alternating short time applications of the erasure signals and checking operations of the erasure state so that the erasure signal application is discontinued when erasure of all informations of the all memory cells is confirmed. In view of prevent even a slight excess erasure state of the memory cells, it is preferable to set the time as short as possible during which the erasure signal is applied to the memory cells. In this case, This leads to a large number of applications of the erasure signals to the memory cells. Such repeat of the application of the high voltage erasure signals many times may cause a deterioration of the erasure properties of the memory cells. The deterioration in the erasure properties of the memory cells requires a longer time application of the high voltage erasure signal to the memory cells. The progress of the deterioration in the erasure properties of the memory cells renders the memory cells approach to a termination of its life-time, resulting in an impossibility of the completion of the erasure of any informations stored in all the memory cells even a possible long time application of the high voltage erasure signal to the memory cells is implemented.
To recognize the life-time of the memory cells, it has already been proposed to count the number of times of the applications of the high voltage erasure signals to the memory cells, one technique of which is disclosed in the Japanese Laid-open Patent Application No. 4-255997. The on-volatile semiconductor memory device with the electrically erasable and programmable read only memory is further provided with a counter for counting the number of times of the erasure/write operations as well as an additional memory for storing the counted number of times thereof. A configuration of this conventional non-volatile semiconductor memory device will hereinafter be described with reference to FIG. 1.
A non-volatile semiconductor memory device 40 includes an electrically erasable and programmable read only memory 1 showing a batch erasure operation wherein all informations stored in all of memory cells provided in the electrically erasable and programmable read only memory 1 are erased one time. The non-volatile semiconductor memory device 40 further includes first and second erasing/writing signals generators 3 and 4, a control unit 30 for controlling operations of individual elements constituting the non-volatile semiconductor device, an erasing/writing times-counter 31 for counting the number of times of the erasure/write operations, an erasing/writing times-memory 32 for storing the counted number of times of the erasure/write operations and an erasure pulse application times-counter 5.
The electrically erasable and programmable read only memory 1 is coupled to a data bus 12 so that informations stored in a specified one in the memory cells comes into a readout to output onto the data bus 12 which is further coupled to a central processing unit 39 as illustrated in FIG. 2. The electrically erasable and programmable read only memory 1 is coupled to the central processing unit 39 to receive a readout instruction signal 10. The electrically erasable and programmable read only memory 1 is also coupled to the control unit 30 to receive a first readout signal 16 and address informations transferred on an internal address bus 15. When the electrically erasable and programmable read only memory 1 receives any one of the readout instruction signal 10 and the first readout signal 16, the electrically erasable and programmable read only memory 1 performs a readout, onto the data bus 12, of an information stored in a memory cell specified according to the address data that the electrically erasable and programmable read only memory 1 received via the internal data bus 15. The electrically erasable and programmable read only memory 1 is also coupled to the first erasing/writing signals generator 3 to receive a first writing signal 21 and a first erasing signal 22. When the electrically erasable and programmable read only memory 1 receives the first writing signal 21, the electrically erasable and programmable read only memory 1 fetches informations on the data bus 12 and stores the fetched informations into a memory cell specified according to the address data that the electrically erasable and programmable read only memory 1 received via the internal data bus 15. When the electrically erasable and programmable read only memory 1 receives the first erasing signal 21, the electrically erasable and programmable read only memory 1 implements the batch erasing operation to erase all informations stored in all the memory cells regardless of the address informations that the electrically erasable and programmable read only memory 1 received via the internal data bus 15.
The control unit 30 is coupled to the central processing unit 39 to receive a writing instruction signal 8 and an erasing instruction signal 9. The control unit 30 is coupled to the central processing unit 39 via an external address bus 11 on which address informations are transferred between the control unit 30 and the central processing unit 39. The control unit 30 is also coupled to the data bus 12 to output the data onto the data bus 12 and fetch the data from the data bus 12. The control unit 30 is coupled to the erasing pulse application times counter 5 to receive erasing pulse application times count data therefrom via a count data bus 25 as well as to supply an initialization signal 13, an erasure control signal 18 and a selective signal 19 independently to the erasing pulse application times counter 5. The selective signals comprise binary digit signals having valid and invalid levels. When the control unit 30 receives no input of the erasing instruction signal 9, the control unit 30 renders address data oft he external address data bus 11 directly output onto the internal address bus 15 on which the address data are transferred into the electrically erasable and programmable read only memory 1. The control unit 30 is further coupled to the first erasing/writing signals generator 3 to supply a writing control signal 17, the erasure control signal 18 and the selective signal 19 into the first erasing/writing signals generator 3. The control unit 30 is furthermore coupled to the second erasing/writing signals generator 4 to supply a writing control signal 17, the erasure control signal 18 and the selective signal 19 into the second erasing/writing signals generator 4. When the control unit 30 receives the input of the write instruction signal 8, the control unit 30 renders the selective signal come into the valid level and further supply the write control signal to the first erasing/writing signals generator 3 for a time corresponding to the predetermined time during which one of the erasing pulse signals is applied to the memory cells in the electrically erasable and programmable read only memory 1. When the control unit 30 receives the input of the erasing instruction signal 9, the control unit 30 shows, with reference to erasure pulse application times data on the count data bus 25, outputs of the address informations onto the internal address bus 15, the first readout signal 16, the write control signal 17, the erasing control signal 18, the selective signal 19, a second readout signal 20, the initialization signal 13, an initial value set signal 33 and an erasure/write completion signal 34. The control unit 30 is coupled to the erasure/write times counter 31 to supply the initial value set signal 33 and the erasure/write completion signals 34 into the erasure/write times counter 31. The control unit 30 is moreover coupled to the erasure/write times memory 32 to supply the second readout signal 20 into the erasure/write times memory 32.
The erasure/write times memory 32 is also coupled to the second erasure/write signals generator 4 to receive both a second write signal 23 and a second erasure signal 24 from the second erasure/write signals generator 4. The erasure/write times memory 32 is further coupled to the erasure/write times counter 31 to supply data, stored therein, as to the erasure/write times, namely the number of times of the erasure/write operations via an internal readout data bus 27 into the erasure/write times counter 31 as well as to receive informations counted by the erasure/write times counter 31 via an internal write data bus 26. The erasure/write times memory 32 is coupled to the central processing unit 39 to receive an erasure/write times readout instruction signal 35. When the erasure/write times memory 32 receives the erasure/write times readout instruction signal 35, the erasure/write times memory 32 shows an output of the data concerned with the onto the internal readout data bus 27. The erasure/write times memory 32 is moreover coupled to the data bus 12 to show an output of the data stored therein onto the data bus 12.
The first erasure/write signals generator 3 shows an output of the first write signal 21 only in a time duration when the selective signal 19 is kept in the valid level and the first erasure/write signals generator 3 is kept to receive an input of the write control signal 17. The first erasure/write signals generator 3 also shows an output of the first erasure signal 22 only in a time duration when the selective signal 19 is kept in the valid level and the first erasure/write signals generator 3 is kept to receive an input of the erasure control signal 18.
The second erasure/write signals generator 4 shows an output of the second write signal 23 only in a time duration when the selective signal 19 is kept in the invalid level and the second erasure/write signals generator 4 is kept to receive an input of the write control signal 17. The second erasure/write signals generator 4 also shows an output of the second erasure signal 24 only in a time duration when the selective signal 19 is kept in the invalid level and the second erasure/write signals generator 4 is kept to receive an input of the erasure control signal 18.
The erasing pulse application times counter 5 initializes the counting data stored therein when receiving the initialization signal 13. The erasing pulse application times counter 5 adds "1" into the existent count data only when the selective signal 19 is kept in the invalid level and the erasure pulse application times counter 5 receives the input of the erasure control signal 18 from the control unit 30. The erasure pulse application times counter 5 keeps to output the data as to the counted number of times of applications of the erasure pulse signals onto the count data bus 25 for keeping the control unit 30 informed of the count data.
When the erasure/write times counter 31 receives an input of the initial value set signal 33 supplied from the control unit 30, the erasure/write times counter 31 initializes data as to the number of times of the erasure/write operations to set the initialized data at the same value of the data fetched via the internal readout data bus 27 from the erasure/write times memory 32 which stores the data as to the counted number of times of the erasure/write operations. The erasure/write times counter 31 adds "1" to the counted data stored therein when receiving an input of the erasure/write completion signal 34. The erasure/write times counter 31 keeps to output the counted data stored therein onto the internal write data bus 26 which is then fetched by the erasure/write times memory 32 for subsequent storing therein.
The erasure/write times memory 32 outputs the data stored therein onto the internal readout data bus 27 when receiving the input of the second readout signal 20. The erasure/write times memory 32 stores the data fetched from the internal write data bus 26 when receiving the input of the second write signal 23. The erasure/write times memory 32 shows an erasure operation of the data stored therein when receiving the input of the second erasure signal 23. The erasure/write times memory 32 also outputs the data stored therein onto the data bus 12 when receiving an erasure/write times readout instruction signal 35 which is supplied from the central processing unit 39.
The following descriptions will focus on the batch erasure operation of the conventional non-volatile semiconductor memory device with reference to FIG. 3 which is illustrative of the steps involved in the batch erasure operations in the form of the flow chart. The batch erasure operation starts and then subsequent operations are implemented.
In a first step S101, the control unit 30 outputs the initialization signal 13 which is then transferred to the erasure pulse application numbers counter 5 thereby the erasure pulse application numbers counter 5 initialize the count data stored therein into "0".
In the second step S102, the control unit 30 outputs the initial value set signal 33 and the second readout signal 20 which are then transferred to the erasure/write times counter 31 and the erasure/write times memory 32 respectively. As a result, the erasure/write times memory 32 outputs the data stored therein onto the internal readout data bus 27 for transferring the data into the erasure/write times counter 31 so that the erasure/write times counter 31 fetches the count data supplied film erasure/write times memory 32 tier subsequent initialization to render the count data stored in the erasure/write times counter 31 correspond to the data fetched film the internal readout data bus 27.
In the third step S103, the control unit 30 switches the selective signal 19 into the valid level and further outputs the erasure control signal 18 fix a predetermined time duration which corresponds to a time unit during which one of the high voltage erasure pulses should be applied to the memory cell in the electrically erasable and programmable read only memory 1. As a result, the first erasure/write control signal generator 3 outputs the first erasure signal 22 only for the unit of the time duration to be transferred to the electrically erasable and programmable read only memory 1 so that the electrically erasable and programmable read only memory 1 performs the erasure operation for the unit of the time duration by application of the high voltage pulse to all of the memory cells provided in the electrically erasable and programmable read only memory 1. At time, the control unit 30 supplies the erasure control signal 18 to the erasure pulse application times counter 5 so that the erasure pulse application times counter 5 performs the counting operation by adding "1" into the counted data stored therein. The erasure pulse application times counter 5 outputs the counted data onto the count data bus 25 so that the currently counted data is kept to be transferred into the control unit 30. This means that the control unit 30 is kept informed of the currently counted data as to the number of times of applications of the high voltage erasure pulse signals.
In the fourth step S104, the control unit 30 outputs data as to a head address as a verify-address concerned with the batch erasure operation onto the internal address bus 15 so that the data as to the head address is then transferred to the electrically erasable and programmable read only memory 1. At the same time, the control unit 30 also outputs the first readout signal 16 which is transferred into the electrically erasable and programmable read only memory 1. At the same time, the control unit 30 also outputs the first readout signal 16 which is transferred into the electrically erasable and programmable read only memory 1.
In the fifth step S105, the electrically erasable and programmable read only memory 1 fetches the head address data of the address bus 15 to specify a memory cell according to the fetched head address data for subsequent output of data stored in the specified memory cell onto the data bus 12. The data of the specified memory cell is then transferred on the data bus 12 to the control unit 30. The control unit 30 fetches the data of the specified memory cell to verify whether the fetched data associated with the specified memory cell would be the erased-data or the data after the erasure was implemented. If the verified data would be the erased-data after the erasure operation, the subsequent step will be the step S106. If the verified data would not be the erased-data, the subsequent step will then be the step S109.
In the sixth step S106, the control unit 30 verifies whether the address data fetched from the internal address bus 15 corresponds to the final address concerned with the batch erasure. If the verified address would be the final address, the subsequent step will be the seventh step S107. If the verified address would not be the final address, the subsequent step will be the step S110.
In the seventh step S107, the control unit 30 outputs the erasure/write completion signal 34 which is then transferred into the erasure/write times counter 31 so that the erasure/write times counter 31 shows the counting operation by adding "1" to the previously counted data stored in the erasure/write times counter 31. After the addition, the erasure/write times counter 31 outputs the currently counted data onto the internal write data bus 26 on which the currently counted data is then transferred to the erasure/write times memory 32 for storing the currently counted data in the erasure/write times memory 32.
In the eighth step S108, the control unit 30 shifts the selective signal 19 into the invalid level as well as outputs the second erasure signal 24 which is transferred into the erasure/write times memory 32 for erasure of the count data stored in the erasure/write times memory 32. The control unit 30 transfers both the invalid level of the selective data 19 and the second write signal 23 into the erasure/write times memory 32. The erasure/write times memory 32 having received the inputs of both the invalid level of the selective data 19 and the second write signal 23 fetches the currently counted data from the internal write data bus 26 for storing the same therein thereby the step S108 is completed. This means that the batch erasure operations are completed.
With reference back to the step S105, if the verified data would not be the erased-data, the process will progress into the step S109. The control unit 30 verifies whether the count data fetched from the count data bus 25 is larger than a predetermined reference number. If the count data is larger than the predetermined reference number it was recognized that the electrically erasable and programmable read only memory 1 be inferior good. As a result, the process currently executing will be discontinued. If the count data is smaller than the predetermined reference number, the process will progress into the step S103. In the step S103, the control unit 30 switches the selective signal 19 into the valid level and further outputs the erasure control signal 18 for a predetermined time duration which corresponds to a time unit during which one of the high voltage erasure pulses should be applied to the memory cell in the electrically erasable and programmable read only memory 1. As a result, the first erasure/write control signal generator 3 outputs the first erasure signal 22 only for the unit of the time duration to be transferred to the electrically erasable and programmable read only memory 1 so that the electrically erasable and programmable read only memory 1 performs the erasure operation for the unit of the time duration by application of the high voltage pulse to all of the memory cells provided in the electrically erasable and programmable read only memory 1. At time, the control unit 30 supplies the erasure control signal 18 to the erasure pulse application times counter 5 so that the erasure pulse application times counter 5 performs the counting operation by adding "1" into the counted data stored therein. The erasure pulse application times counter 5 outputs the counted data onto the count data bus 25 so that the currently counted data is kept to be transferred into the control unit 30. This means that the control unit 30 is kept informed of the currently counted data as to the number of times of applications of the high voltage erasure pulse signals. The subsequent steps are the fourth and fifth steps S104 and S105.
With reference back to the step S106, if the verified address would not be the final address, the process will progress into the step 110 in which the control unit 30 performs an increment of the verify-address by adding the verify-address with one address and thereafter the control unit 30 outputs the address data having received the increment with one address onto the internal address bus 15 so that the incremented address data is transferred into the electrically erasable and programmable read only memory 1 to thereby progress into the step S105. In the step 105, the electrically erasable and programmable read only memory 1 fetches the incremented address data of the internal address bus 15 to specify a memory cell according to the incremented address data for subsequent output of data stored in the specified memory cell onto the data bus 12. The data of the specified memory cell is then transferred on the data bus 12 to the control unit 30. The control unit 30 fetches the data of the specified memory cell to verily whether the fetched data associated with the specified memory cell would be the erased-data or the data after the erasure was implemented. If the verified data would be the erased-data after the erasure operation, the subsequent step will be the step S106. If the verified data would not be the erased-data, the subsequent step will then be the step S109.
As a result of the foregoing processes, the batch erasure operation is completed. The counted total number of times of the erasure/write operations is then stored in the erasure/write times memory 32. The central processing unit 39 supplies the erasure/write times readout instruction signal 35 to the erasure/write times memory 32 thereby the erasure/write times memory 32 outputs the total number of times of the erasure/write operations stored therein onto the data bus 12 so that the data as to the total number of times of the erasure/write operations are transferred to the central processing unit 39.
The above structure of the conventional non-volatile semiconductor memory 40 has the provisions of the erasure/write times counter 31 for counting the number of times of the erasure/write operations and the erasure/write times memory 32 for storing the counted data associated with the number of times of the erasure/write operations so as to detect a deterioration, due to the repeat of a number of times of the erasure/write operations, of the property of the electrically erasable and programmable read only memory 1. The above structure is designed to allow the output of the above data of the total count number onto the data bus so as to permit the readout thereof by the central processing unit 39. Those result in a certain reduction in a burden of the central processing unit 39 in management of the number of times of the erasure/write operations associated with the electrically erasable and programmable read only memory 1.
The above non-volatile semiconductor memory 40 would be required to implement repeats a number of times of alternations of the high voltage erasure signal applications for the short unit time duration and subsequent verifying process for verifying whether there has already been erased informations or data stored in all of the memory cells in the electrically erasable and programmable read only memory 1.
Actually, however, a considerably large number of times of applications of the high voltage pulse signals for the short unit time duration are required. It may be assumed that the unit time duration is 10 milliseconds, the averaged number of times of the repeats of the alternations of the high voltage erasure signal applications processes and subsequent verifying process is 50, a time necessary for the readout operation of one word is 1 microsecond and an address area to be subjected to the batch erasure has 16 Chords wherein 1K=1024. The averaged time necessary for verifying one time the erasure states of all the memory cells is given by the following equation, namely 10 milliseconds. EQU (1/2).times.(1 .mu.s).times.(16K)=10 ms. (1)
The averaged time necessary for the batch erasure operation is given by the following equation, namely about 1000 milliseconds. EQU (10 ms+10 ms).times.50=1000 ms. (2)
The time necessary for verifying the erasure states of all the memory cells occupies about 50% of the time necessary for the batch erasure operation. This may largely contribute the enlargement of the time necessary for the batch erasure operation.
On the other hands, the requirement for improvement in high speed erasure and write operations of the non-volatile semiconductor memory device has been on the increase. Under such circumstances, it has seriously been required to develop a new technique for a possible reduction of the time necessary for the batch erasure operations.